Lead DFT Engineer: SoC Test & Validation

Rivian; Palo Alto (CA); On-site; USD 186,000 - 232,000; Full time

Benefits offered by this job

401(k) plan

Employee Stock Purchase Program

Comprehensive health benefits (medical

Job summary

Rivian is seeking an experienced DFT Engineer to define, implement, and deploy advanced Design-for-Test methodologies across RTL to post-silicon stages. You will own DFT insertion, verification, and test coverage closure, collaborating with Front-end RTL, Physical Design, and Productization teams.

The role requires 5+ years in DFT for SoCs, strong scripting skills, and hands-on experience with Scan, MBIST, TAP, and ATPG flows.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent experience.
• 5+ years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience in DFT flow, including architecture, IP integration (e.g., Scan controllers, TAP, MBIST), and interaction with synthesis and verification flows.
• Experience with industry-leading EDA tools for DFT, such as Synopsys Fusion Compiler, TestMax or Siemens Tessent.

Responsibilities

• Lead implementation of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, logic BIST, Functional Safety(FuSa) and Analog IP Tests.
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of DFT fabrics and IP within Subsystems
• Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl
• Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, Cell- aware, path delay fault models, diagnosis, and hierarchical test flows.
• Run and debug non-timing and SDF annotated gate level simulations
• Analyze test results and drive test coverage improvement and closure
• Develop ,validate and timing closure of DFT timing constraints for scan, BIST, and test modes
• Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
• Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up, debug and Silicon characterization
• Exposure to mixed-signal or SERDES DFT, such as IOBIST or loopback testing
• Exposure to Chiplet-based architectures, including Die-to-Die (D2D) test methodologies (e.g., UCIe interfaces) and Known Good Die (KGD) strategies.

Skills

DFT architecture

ATPG

RTL concepts

Scripting (Perl/Python/Tcl)

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent experience

Tools

Synopsys Fusion Compiler

Synopsys TestMax

Siemens EDA Tessent

TAP / MBIST tools

Job description

Rivian is seeking an experienced DFT Engineer to define, implement, and deploy advanced Design-for-Test methodologies across RTL to post-silicon stages. You will own DFT insertion, verification, and test coverage closure, collaborating with Front-end RTL, Physical Design, and Productization teams.

The role requires 5+ years in DFT for SoCs, strong scripting skills, and hands-on experience with Scan, MBIST, TAP, and ATPG flows.