Senior DFT-Driven ASIC Verification Engineer

Meta; Austin (TX); Presencial; USD 178.000 - 250.000; Jornada completa

Descripción de la vacante

Meta in Austin, Texas, seeks an ASIC Design Verification Engineer specialized in DFT to drive verification closure for data-center silicon. You will develop DFT architectures, build UVM testbenches, and ensure testability and manufacturability across IP, sub-system, and SoC levels.

You will collaborate with Design, DFT Architecture, Emulation, and Post-Silicon Validation teams to validate scan, BIST, JTAG, and related structures using simulation, formal analysis, and emulation-based verification

Formación

• 8+ years of hands-on ASIC design verification experience.
• Proficient in SystemVerilog and UVM-based methodologies.
• Experience with DFT verification including scan insertion, ATPG, BIST, and JTAG.
• Strong scripting for verification flow automation (Python, Tcl, Perl, Shell).

Responsabilidades

• Define and implement DFT verification plans across IP, sub-system, and SoC levels.
• Develop and maintain UVM-based testbenches to verify DFT logic.
• Drive verification closure using functional, code, and DFT-specific coverage metrics.
• Collaborate with DFT architects and design engineers to review insertion methodologies.
• Debug and root-cause functional and structural failures in DFT logic pre-silicon.

Conocimientos

SystemVerilog

UVM

DFT verification

SoC verification

IP verification

Herramientas

Python

Tcl

Perl

Shell

Descripción del empleo

Meta in Austin, Texas, seeks an ASIC Design Verification Engineer specialized in DFT to drive verification closure for data-center silicon. You will develop DFT architectures, build UVM testbenches, and ensure testability and manufacturability across IP, sub-system, and SoC levels.

You will collaborate with Design, DFT Architecture, Emulation, and Post-Silicon Validation teams to validate scan, BIST, JTAG, and related structures using simulation, formal analysis, and emulation-based verification