Senior ASIC DFT Verification Engineer with UVM & ATPG

Anysilicon; Sunnyvale (CA); Hybrid; USD 140.000 - 210.000; Vollzeit

Zusammenfassung

Meta is seeking an experienced ASIC Design Verification Engineer specializing in DFT to join its Infrastructure Silicon organization in Sunnyvale, CA. The role focuses on developing and verifying DFT architectures for custom ASICs and SoCs used in data center infrastructure.

You will define DFT verification plans, build UVM-based testbenches, and drive coverage acceptance while collaborating with DFT architects and design teams to ensure robust, testable silicon.

Qualifikationen

• 6 years hands-on ASIC design verification experience.
• Strong DFT verification experience including scan insertion and ATPG.
• Proficient in SystemVerilog, UVM, and scripting (Python, Tcl, Perl, or Shell).

Aufgaben

• Define and implement DFT verification plans for scan insertion, ATPG, BIST, JTAG, and boundary scan structures.
• Develop and maintain UVM-based and C/C++ testbenches for DFT logic verification.
• Drive verification closure using functional coverage and DFT-specific structural coverage.
• Collaborate with DFT architects and design engineers to validate DFT insertion methodologies.
• Debug and root-cause functional and structural failures in DFT logic.
• Develop ATPG test pattern generation flows meeting quality and fault coverage targets.
• Apply formal verification techniques to DFT control logic and test mode isolation.
• Partner with emulation and post-silicon validation teams for DFT bring-up and correlation.

Kenntnisse

DFT verification

SystemVerilog

UVM

Python scripting

Tools

EDA tools for DFT insertion and simulation

Jobbeschreibung

Meta is seeking an experienced ASIC Design Verification Engineer specializing in DFT to join its Infrastructure Silicon organization in Sunnyvale, CA. The role focuses on developing and verifying DFT architectures for custom ASICs and SoCs used in data center infrastructure.

You will define DFT verification plans, build UVM-based testbenches, and drive coverage acceptance while collaborating with DFT architects and design teams to ensure robust, testable silicon.