Remote-Eligible Senior DFT Verification Engineer

Delos Data Inc; Palo Alto (CA); Hybrid; USD 160,000 - 230,000; Full time

Job summary

Delos Data Inc., based in Silicon Valley with a mix of remote and on-site work, seeks a Senior DFT Verification Engineer to build robust verification environments for ASIC DFT logic. You will drive coverage-driven verification, collaborate with DFT and manufacturing teams, and contribute to pre-silicon MBIST/scan testing using TestMax and Tessent.

The role requires deep SystemVerilog/UVM expertise, gate-level concepts, and scripting in Python to automate regression and enhance verification

Qualifications

• Bachelor's or master's degree in EE/CE.
• 5+ years in digital design verification, 2+ in DFT verification.
• Hands-on with UVM-based verification.
• Proficient in SystemVerilog and Python scripting.
• Experience with industry-standard EDA and DFT tools.

Responsibilities

• Develop, implement, and maintain RTL verification environments using UVM or equivalent.
• Create and execute coverage-driven verification plans.
• Use EDA DFT tools to create and run pre-silicon test cases for MBIST and scan fabric.
• Develop directed tests for non-vendor DFT logic to validate functionality.
• Assist in verifying ATPG patterns at SOC level and manufacturing reset sequences.
• Analyze simulation results and perform root-cause analysis with DFT engineers.
• Implement and track functional and code coverage to drive closure.
• Write SystemVerilog Assertions (SVA) and develop reusable verification components.
• Participate in design and verification reviews; automate regression testing with Python.
• Contribute to process/tooling improvements and post-silicon test support.

Skills

SystemVerilog

UVM verification

Python scripting

Gate-level verification

DFT concepts

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys VCS

Mentor Questa

Cadence Xcelium

TestMax

Tessent

Job description

Delos Data Inc., based in Silicon Valley with a mix of remote and on-site work, seeks a Senior DFT Verification Engineer to build robust verification environments for ASIC DFT logic. You will drive coverage-driven verification, collaborate with DFT and manufacturing teams, and contribute to pre-silicon MBIST/scan testing using TestMax and Tessent.

The role requires deep SystemVerilog/UVM expertise, gate-level concepts, and scripting in Python to automate regression and enhance verification