Senior DFT ASIC Engineer: Testability & Bring-Up

Meta Careers; Sunnyvale, Northern (CA, KY); Hybrid; USD 150,000 - 210,000; Full time

Job summary

Meta in Sunnyvale, CA is hiring an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team.

You will architect DFT strategies from RTL through silicon bring-up, implementing scan insertion, ATPG, MBIST, LBIST, and boundary scan for large-scale infrastructure ASICs, and collaborate with design, physical implementation, and validation teams to meet aggressive quality and time-to-market targets.

Qualifications

• DFT architectures including scan insertion, ATPG, MBIST/LBIST, and boundary scan for large-scale infrastructure ASICs.
• Flows and methodologies from RTL through tape-out with timing/area constraints.
• Fault-model coverage targets and post-silicon diagnosis support.

Responsibilities

• Define and implement comprehensive DFT architectures including scan insertion, ATPG, MBIST, LBIST, and boundary scan for large-scale infrastructure ASICs
• Develop and drive DFT methodology and flows from RTL through tape-out, including scan compression, test point insertion, and clock domain handling
• Generate, simulate, and validate ATPG test patterns to achieve target fault coverage across stuck-at, transition, path delay, and cell-aware fault models
• Collaborate with physical design teams to ensure DFT structures meet timing, area, and power constraints during implementation
• Partner with silicon validation and manufacturing test teams to define ATE test programs and support post-silicon debug and diagnosis
• Perform DFT sign-off including fault coverage analysis, test coverage reporting, and DRC/LVS compliance for testability structures
• Develop and maintain DFT scripts and automation to improve flow efficiency, reduce manual effort, and enable reuse across chip generations

Skills

DFT architectures

ATPG

MBIST

LBIST

Boundary scan

Scan insertion

RTL flows

Automation scripting

Job description

Meta in Sunnyvale, CA is hiring an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team.

You will architect DFT strategies from RTL through silicon bring-up, implementing scan insertion, ATPG, MBIST, LBIST, and boundary scan for large-scale infrastructure ASICs, and collaborate with design, physical implementation, and validation teams to meet aggressive quality and time-to-market targets.