Senior ASIC DFT Verification Engineer (IP/SoC)

Meta; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta is hiring an ASIC Design Verification Engineer specializing in DFT within the Infrastructure Silicon organization. We are looking for experienced engineers to develop and verify DFT architectures for custom ASICs and SoC designs powering Meta's data center infrastructure.

You will drive DFT verification closure across IP, sub-system, and SoC levels, ensuring silicon manufacturability, testability, and quality for first-pass success. Collaboration with multiple teams is essential.

Qualifications

• Bachelor's degree in CS/CE or equivalent practical experience.
• 6+ years of ASIC design verification using SystemVerilog and UVM-based methodologies.
• 6+ years of DFT verification including scan insertion, ATPG, BIST and JTAG/IEEE 1149.1.
• Experience with EDA tools for DFT insertion, ATPG, and simulation; scripting in Python, Tcl, Perl or Shell.
• Experience driving IP/sub-system/SoC verification closure including test planning, testbench development and coverage analysis.

Responsibilities

• Define and implement DFT verification plans covering scan insertion, ATPG, BIST, JTAG, and boundary scan structures at IP, sub-system, and SoC levels
• Develop and maintain UVM-based and C/C++-based testbenches to verify DFT logic, including scan chains, memory BIST, and logic BIST controllers
• Drive verification closure using functional coverage, code coverage, and DFT-specific structural coverage goals
• Collaborate with DFT architects and design engineers to review DFT insertion methodologies and validate scan stitching and test access
• Debug and root-cause functional and structural failures in DFT logic with design and ATPG teams pre-silicon
• Develop and validate ATPG test pattern generation flows, ensuring pattern quality and fault coverage targets
• Apply formal verification techniques to prove correctness of DFT control logic, scan enable paths, and test mode isolation
• Partner with emulation and post-silicon validation teams to enable DFT bring-up and correlate pre-silicon results with silicon tests
• Build and maintain verification infrastructure, scripts, and automation flows to improve DFT verification efficiency
• Contribute to continuous improvement of DFT verification methodologies, tools, and best practices

Skills

SystemVerilog

UVM

ATPG

BIST

JTAG

Python scripting

Education

Bachelor's degree in Computer Science, Computer Engineering, or equivalent

Job description

Meta is hiring an ASIC Design Verification Engineer specializing in DFT within the Infrastructure Silicon organization. We are looking for experienced engineers to develop and verify DFT architectures for custom ASICs and SoC designs powering Meta's data center infrastructure.

You will drive DFT verification closure across IP, sub-system, and SoC levels, ensuring silicon manufacturability, testability, and quality for first-pass success. Collaboration with multiple teams is essential.