Senior DFT/DFM ASIC Engineer - ATPG & Customer Tech Lead

Intel Corporation; Chandler (AZ); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Competitive compensation

Stock bonuses

Health benefits

Professional development

Job summary

Intel Foundry Services seeks a Senior DFT Logic Design Engineer in Phoenix, AZ for hybrid on-site/off-site delivery. You will drive DFT/DFM insertion, ATPG validation, and collaborate with customers, IP providers, and vendors to resolve issues and enable successful tape-outs.

Requirements include a BS in Electrical/Computer Engineering or related field, 3+ years in CMOS processes, 3+ years in ASIC DFT/DFM, and 4+ years scripting (Python/Perl/Tcl/sh).

Qualifications

• Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
• 3+ years of experience with advanced CMOS processes (16nm and below)
• 3+ years of experience in implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG, …) at ASIC design block level and at full chip level. Performing ATPG validation and DFT timing and DFT signoff at SOC level.
• 4+ years of experience in one or more of the following scripting languages e.g. Python, Perl, Tcl, and/or shell scripting.

Responsibilities

• Collaborate with internal teams across Intel and external stakeholders such as foundry customers’ design teams, IP providers, and EDA vendors on issue resolution.
• Create content, application notes and deliver technical training/presentations.
• Drive quality of ASIC DFT/DFM and ATPG validation methodology, capability/flow and documentation for block level and SOC level.
• Support and provide Tool/Flow/Methodology on customer issues and challenges for successful customer tape-outs, and to increase customer satisfaction.

Skills

CMOS process experience

ATPG validation

Scripting languages (Python, Perl, Tcl

Customer facing experience

Education

Bachelor's degree in Electrical/Computer Engineering or related STEM field

Tools

EDA tools suites for MBIST/SCAN/JTAG

DFT/DFM insertion tooling

Job description

Intel Foundry Services seeks a Senior DFT Logic Design Engineer in Phoenix, AZ for hybrid on-site/off-site delivery. You will drive DFT/DFM insertion, ATPG validation, and collaborate with customers, IP providers, and vendors to resolve issues and enable successful tape-outs.

Requirements include a BS in Electrical/Computer Engineering or related field, 3+ years in CMOS processes, 3+ years in ASIC DFT/DFM, and 4+ years scripting (Python/Perl/Tcl/sh).