Senior DFT/ATPG Logic Design Engineer — Hybrid

Intel Corporation

Santa Clara (CA)

Hybrid

USD 142,000 - 269,000

Full time

14 days+

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Benefits offered by this job

Stock bonuses
Health benefits
Vacation
Hybrid work model

Job summary

Intel Foundry is seeking a Senior DFT Logic Design Engineer to provide technical support on PDKs, DFT/DFM insertion, and ATPG validation for ADG customers. You will collaborate with internal teams and external customers to drive ASIC DFT quality and successful tape-outs.

The role requires a strong background in CMOS processes, scripting, and experience with EDA tools. This hybrid position offers exposure to cutting-edge semiconductor technology and national security implications.

Qualifications

  • US Citizenship required.

Responsibilities

  • Collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on issue resolution.
  • Create content, application notes and deliver technical training/presentations.
  • Drive quality of ASIC DFT/DFM and ATPG validation methodology, capability/flow and documentation for block level and SOC level.
  • Support and provide Tool/Flow/Methodology on customer issues and challenges for successful customer tape-outs, and to increase customer satisfaction.

Skills

DFT/DFM insertion
ATPG validation
Scripting languages
ASIC design
Full chip level ATPG
Customer-facing
Communication skills
Team collaboration

Education

Bachelor's degree in Electrical / Computer Engineering or Computer Science

Tools

MBIST tooling
JTAG tooling
DFT/DFX tooling

Job description

Intel Foundry is seeking a Senior DFT Logic Design Engineer to provide technical support on PDKs, DFT/DFM insertion, and ATPG validation for ADG customers. You will collaborate with internal teams and external customers to drive ASIC DFT quality and successful tape-outs.

The role requires a strong background in CMOS processes, scripting, and experience with EDA tools. This hybrid position offers exposure to cutting-edge semiconductor technology and national security implications.

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