Senior DFT Lead: ASIC Test & Post-Silicon Validation

itD Tech; United States; Hybrid; USD 150,000 - 190,000; Full time

Benefits offered by this job

Medical benefits

401k plan

Paid holidays

Job summary

itD seeks a DFT Lead to drive advanced DFT solutions across the silicon development lifecycle. You will ensure highly testable, manufacturable ASIC designs and lead test architecture development.

Responsibilities include post-silicon debugging, production qualification, and collaboration with design, validation, and hardware teams. Ideal candidates have 8–10+ years in ASIC DFT, hands-on experience with JTAG, MBIST, boundary scan, and ATPG tools.

Qualifications

• 8–10+ years of ASIC DFT engineering experience.
• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field.
• Hands-on with JTAG, scan, MBIST, BISR, boundary scan, and third‑party IP integration.

Responsibilities

• Lead hardware DFT features deployment: scan, MBIST, BISR, boundary scan, and DFT sim setup.
• Develop DFT IP with cross-functional teams and integrate testability into RTL.
• Drive reusable DFT methods for next-gen silicon, including bare die and stacked die.
• Post-silicon debugging, root-cause analysis, and production qualification to boost yield.

Skills

DFT engineering

ASIC design

Post-silicon debugging

ATPG/MBIST

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

Tessent

Xcelium

Genus

Tempus or PrimeTime

Job description

itD seeks a DFT Lead to drive advanced DFT solutions across the silicon development lifecycle. You will ensure highly testable, manufacturable ASIC designs and lead test architecture development.

Responsibilities include post-silicon debugging, production qualification, and collaboration with design, validation, and hardware teams. Ideal candidates have 8–10+ years in ASIC DFT, hands-on experience with JTAG, MBIST, boundary scan, and ATPG tools.