ASIC Design-for-Test (DFT)

Accord Technologies Inc; San Jose (CA); On-site; USD 150,000 - 200,000; Full time

Job summary

Accord Technologies Inc is looking for a Lead ASIC DFT Engineer in San Jose, CA. The role involves architecting, implementing, verifying, and debugging advanced DFT solutions for complex ASIC designs. Candidates must have over 10 years of hands-on DFT experience, including scan insertion and ATPG. Strong expertise in silicon debug and the EDA tools like Synopsys and Cadence is desired. The position is remote and accommodates employees in the PST time zone.

Qualifications

• 10+ years of hands-on experience in ASIC Design-for-Test (DFT).
• Strong hands-on ASIC DFT experience with end-to-end ownership.
• Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.

Responsibilities

• Architect, implement, verify, and debug advanced DFT solutions for ASIC and SoC designs.
• Lead cross-functional debug efforts and drive resolution of critical silicon issues.

Skills

DFT Architecture definition

Full chip / Sub system level DFT activities

Scan & compression (EDT) implementation

LBIST implementation and verification

ATPG

TCL scripting

PERL scripting

Python scripting

Tools

Synopsys

Cadence

Siemens/Mentor EDA tools

Job description

Lead ASIC DFT Engineer

Location: San Jose, CA

Work Setup: Remote, PST time zone

Number of openings: 4 positions

Visa type: Any Visa that can work in PST time zone

Position type: W2 or C2C

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post‑silicon validation, along with the ability to lead cross‑functional debug efforts and drive resolution of critical silicon issues.

Experience Required

• 10+ years of hands‑on experience in ASIC Design‑for‑Test (DFT)

Mandatory Skills

• DFT Architecture definition – Must
• Full chip / Sub system level DFT activities – Must
• Scan & compression (EDT) implementation
• LBIST implementation and verification – any BIST experience
• Coverage improvements (Spyglass work)
• ATPG

Key Skills

• Strong hands‑on ASIC DFT experience with end‑to‑end ownership
• Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
• Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
• Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
• MBIST implementation and verification; SMS experience preferred
• Tessent/SSN experience preferred
• Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
• Post‑silicon debug and silicon bring‑up experience

Skill Metrics Required

• TCL, PERL, or Python scripting experience is highly preferred
• DFT Architecture
• Scan & compression (EDT) implementation
• LBIST implementation and verification
• Coverage improvements (Spyglass work)
• ATPG sims – timing & no timing
• Full chip / Sub system level DFT activities