Senior DFT Logic Design Engineer — Hybrid ASIC Lead

Intel; Phoenix (AZ); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Cutting-edge DFT tech

Direct customer engagement

Professional DFT/DFX training

Job summary

Intel Foundry is seeking a Senior DFT Logic Design Engineer to support Aerospace/Defense/Gov customers, focusing on DFT/DFM insertion, ATPG validation, and flow development. You will collaborate with customers, IP providers, and EDA vendors to resolve issues and provide technical training.

The role requires a Bachelor's in a STEM field, 3+ years in CMOS processes, and scripting skills, with a hybrid work model in the United States. U.S. government security clearance is preferred.

Qualifications

• US Citizenship required and ability to obtain government security clearance.
• Bachelor's degree in Electrical/Computer Engineering, Computer Science or STEM field.
• 3+ years in advanced CMOS processes (16nm and below).
• 3+ years implementing ASIC DFT/DFM insertion and ATPG validation at block and SOC levels.
• 4+ years scripting in Python, Perl, Tcl, or shell.

Responsibilities

• Collaborate with internal/external teams including customers, IP providers and EDA vendors on issue resolution.
• Create content, application notes and deliver technical training/presentations.
• Drive DFT/DFM/ATPG validation methodology, flows, and documentation for block and SOC levels.
• Support customer tape-outs with tool/flow/methodology insights to improve satisfaction.

Skills

US Citizenship

Security clearance eligibility

CMOS processes

DFT/DFM implementation

Scripting languages

Education

Bachelor's in ECE/CS/STEM

Tools

MBIST

LBIST

JTAG

ATPG

Job description

Intel Foundry is seeking a Senior DFT Logic Design Engineer to support Aerospace/Defense/Gov customers, focusing on DFT/DFM insertion, ATPG validation, and flow development. You will collaborate with customers, IP providers, and EDA vendors to resolve issues and provide technical training.

The role requires a Bachelor's in a STEM field, 3+ years in CMOS processes, and scripting skills, with a hybrid work model in the United States. U.S. government security clearance is preferred.