Senior ASIC DFT Engineer — Post-Silicon Bringup & Test

United States Digital Space LLC; Austin (CA); On-site; USD 165,000 - 260,000; Full time

Benefits offered by this job

Stock options

Long-term incentives

Medical, vision, dental insurance

401(k)

Paid vacation

Paid holidays

Job summary

United States Digital Space LLC is seeking a Sr. ASIC DFT Engineer to design and optimize DFT architectures for next‑generation ASICs used in space and ground infrastructure.

You will implement scan insertion, memory BIST, and logic BIST, and lead ATPG pattern development with Siemens Tessent tools. You will collaborate with cross‑functional teams, verify DFT IPs, and run non‑timing/gate‑level simulations while developing automation scripts in Perl/Python/Tcl/C++.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or physics.
• 5+ years of experience in semiconductor Design For Test (DFT) engineering, post‑silicon validation, and/or production testing.

Responsibilities

• Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools.
• Integration and verification of DFT IPs and fabrics within Subsystems.
• Set up and run ATPG tools and methodologies, including patterns for stuck‑at, transition, and path delay fault models, with focus on compression, diagnosis, and hierarchical test flows.
• Run and debug non‑timing and SDF annotated gate‑level simulations.
• Create and validate DFT patterns for post‑silicon bringup and assist with ATE debug through silicon characterization cycles.
• Develop test scripts, automate processes, and analyze data using Perl, Python, Tcl, or C++.

Skills

DFT design

ASIC

ATPG

Siemens Tessent

Scripting (Perl, Python, Tcl, C++)

Testability standards

Education

Bachelor’s degree in electrical engineering, computer engineering, or physics

Tools

Siemens Tessent

Teradyne

Advantest

Job description

United States Digital Space LLC is seeking a Sr. ASIC DFT Engineer to design and optimize DFT architectures for next‑generation ASICs used in space and ground infrastructure.

You will implement scan insertion, memory BIST, and logic BIST, and lead ATPG pattern development with Siemens Tessent tools. You will collaborate with cross‑functional teams, verify DFT IPs, and run non‑timing/gate‑level simulations while developing automation scripts in Perl/Python/Tcl/C++.