Senior DFT & ASIC Logic Design Engineer - Hybrid

Intel; Hillsboro (OR); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Hybrid work model

Competitive compensation

Stock bonuses

Health benefits

Professional development

Job summary

Intel Foundry is seeking a Senior DFT Logic Design Engineer to join the Aerospace, Defense, Government team. You will collaborate with internal teams and customers to advance DFT/DFM and ATPG validation across blocks and SOC.

The role requires US citizenship, ability to obtain clearance, and 3+ years CMOS/DFT experience; hybrid work in the US with sites including Hillsboro, OR. Join us to influence silicon design for the AI era.

Qualifications

• US Citizenship required and ability to obtain clearance.
• Bachelor's degree in Electrical/Computer Engineering, CS or STEM.
• 3+ years CMOS/DFT/ATPG experience at ASIC/SOC level.

Responsibilities

• Collaborate with internal teams and external stakeholders on issue resolution.
• Create content, notes and deliver technical training.
• Drive DFT/DFM and ATPG validation methodology and documentation.
• Support tool/flow/methodology for customer tape-outs and satisfaction.

Skills

CMOS process experience

DFT/DFM insertion

ATPG validation

Scripting: Python/Perl/Tcl

Education

Bachelor's degree in Electrical / Computer Engineering or STEM

Postgraduate degree preferred

Tools

MBIST

LBIST

JTAG

Job description

Intel Foundry is seeking a Senior DFT Logic Design Engineer to join the Aerospace, Defense, Government team. You will collaborate with internal teams and customers to advance DFT/DFM and ATPG validation across blocks and SOC.

The role requires US citizenship, ability to obtain clearance, and 3+ years CMOS/DFT experience; hybrid work in the US with sites including Hillsboro, OR. Join us to influence silicon design for the AI era.