Senior DFT Design Engineer for Next‑Gen ICs

Altera Corporation; San Jose (CA); Hybrid; USD 187,000 - 271,000; Full time

Job summary

Altera Corporation in San Jose, CA, is seeking a Senior DFT Design Engineer to define DFT architectures and implement test logic for FPGA, processors, DSP, SERDES, IO, and multi-die designs. You will perform ATPG pattern generation and pre-silicon validation to ensure manufacturability and quality.

You will collaborate with IP and integration teams to align DFT features with timing and functionality, and work with test development to support silicon bring-up, debug, and production readiness.

Qualifications

• 8+ years of experience in DFT design and verification at RTL and gate level.
• Experience with synthesis and scan insertion tools, ATPG tools, simulation and debug tools, STA tools.
• Scripting languages such as Perl and TCL

Responsibilities

• Define and implement DFT architectures and specifications for FPGA, processors, DSP, SERDES, IO, and multi-die designs.
• Perform test logic insertion, ATPG pattern generation, and pre-silicon validation for manufacturability and quality.
• Collaborate with IP and integration design teams to align DFT features with design functionality and timing.
• Partner with test development teams to support silicon bring-up, debug, and production readiness.
• Contribute to DFT methodology and automation flows to enhance scalability and efficiency.
• Ensure manufacturability goals are met, including test coverage, test cost optimization, yield improvement, and debug support.

Skills

DFT design & verification

RTL & gate-level testing

Perl/TCL scripting

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Master’s degree in Electrical Engineering or Computer Engineering

Tools

Synthesis tools

ATPG tools

Simulation & debug tools

STA tools

Job description

Altera Corporation in San Jose, CA, is seeking a Senior DFT Design Engineer to define DFT architectures and implement test logic for FPGA, processors, DSP, SERDES, IO, and multi-die designs. You will perform ATPG pattern generation and pre-silicon validation to ensure manufacturability and quality.

You will collaborate with IP and integration teams to align DFT features with timing and functionality, and work with test development to support silicon bring-up, debug, and production readiness.