Senior DFT Design Engineer

191 Altera Corporation

San Jose (CA)

Presencial

USD 187.000 - 271.000

Jornada completa

14 días+

Una candidatura completa en un minuto

Currículum y carta de presentación personalizados, listos para enviar.

Supera los filtros ATS

Descripción de la vacante

Altera is seeking a Senior DFT Design Engineer in San Jose, CA to lead DFT architecture, insertion, and pre-silicon validation for FPGA, processors, DSP, and high-speed IO/SerDes designs.

You will collaborate with IP and test teams to ensure manufacturability, yield, and test coverage while driving scalable DFT methodologies and automation across complex silicon.

Formación

  • Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 10+ years of industry experience OR Master's degree with 8+ years of experience.
  • 8+ years of experience in DFT design and verification at RTL and gate level.
  • Experience with EDA tools: synthesis, scan insertion, ATPG, simulation, and debug; scripting in Perl/TCL.
  • Preferred qualifications: experience with test compression, MBIST/LBIST, and advanced fault models.
  • Prior experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT.

Responsabilidades

  • Define and implement DFT architectures and specifications for FPGA, processors, DSP, SERDES, IO, and multi-die designs.
  • Perform test logic insertion, ATPG pattern generation, and pre-silicon validation for manufacturability and quality.
  • Collaborate with IP and integration design teams to align DFT features with design functionality and timing.
  • Partner with test development teams to support silicon bring-up, debug, and production readiness.
  • Contribute to DFT methodology and automation flows to enhance scalability and efficiency.
  • Ensure manufacturability goals are met, including test coverage, cost optimization, yield improvement, and debug support.

Conocimientos

DFT design & verification
RTL & gate-level
Scripting: Perl/TCL
EDA tools proficiency
DFT methodology & automation

Educación

Bachelor's degree in Electrical Engineering or Computer Engineering
Master's degree in Electrical/Computer Engineering

Herramientas

Synthesis tools
ATPG tools
Simulation & debug tools
STA tools
Design automation scripting

Descripción del empleo

About the Role

The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization. This is an opportunity to work on cutting-edge technologies including FPGA, processor, DSP, SERDES, IO, 2.5D/3D multi-die packaging, and other advanced solutions that will drive future innovation. As a Senior DFT Design Engineer, you will be responsible for DFT architecture and implementation, including DFT specifications, test logic insertion, test mode timing constraints, ATPG, and pre-silicon validation. You will also contribute to the development of DFT methodologies and flows to improve pre-silicon and post-silicon validation processes. This role provides the opportunity to work closely with IP and integration design teams to understand design and functional behaviors of complex circuits, as well as with test development teams to meet manufacturing test requirements for coverage, cost, yield, and silicon bring-up/debug.

Responsibilities
  • Define and implement DFT architectures and specifications for FPGA, processors, DSP, SERDES, IO, and multi-die designs.
  • Perform test logic insertion, ATPG pattern generation, and pre-silicon validation for manufacturability and quality.
  • Collaborate with IP and integration design teams to align DFT features with design functionality and timing.
  • Partner with test development teams to support silicon bring-up, debug, and production readiness.
  • Contribute to DFT methodology and automation flows to enhance scalability and efficiency.
  • Ensure manufacturability goals are met, including test coverage, test cost optimization, yield improvement, and debug support.
Salary Range

Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $187,000 - $270,700 USD We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Qualifications
  • Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 10+ years of industry experience in the following - OR - Master's degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of industry experience in the following:
  • 8+ years of experience in DFT design and verification at both RTL and gate level.
  • Experience in EDA tools such as synthesis and scan insertion tools, ATPG tools, simulation and debug tools, STA tools Design automation experience and proficiency in scripting languages such as Perl/TCL.
  • Preferred Qualifications: Experience with test compression, BIST (MBIST/LBIST), and advanced fault models.
  • Prior experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT.
Job Type

Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance.

About Altera

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.

Consigue la evaluación confidencial y gratuita de tu currículum.

o arrastra y suelta tu archivo aquí

Similar jobs

Puestos de trabajo similares que vale la pena comparar

Senior DFT Design Engineer
Senior DFT Design Engineer

Altera • San Jose (CA)

Presencial
USD 187.000 - 271.000
FPGA System Design Engineer
FPGA System Design Engineer

191 Altera Corporation • San Jose (CA)

Presencial
USD 119.000 - 172.000
Senior Physical Design Engineer
Senior Physical Design Engineer

191 Altera Corporation • San Jose (CA)

Presencial
USD 133.000 - 193.000
Physical Design Engineer
Physical Design Engineer

191 Altera Corporation • San Jose (CA)

Presencial
USD 133.000 - 193.000
EDA Software Engineer
EDA Software Engineer

191 Altera Corporation • San Jose (CA)

Presencial
USD 149.000 - 216.000
Senior DFT Design Engineer for Next‑Gen ICs
Senior DFT Design Engineer for Next‑Gen ICs

Altera Corporation • San Jose (CA)

Híbrido
USD 187.000 - 271.000
Full Chip Timing Modeling and Integration Engineer
Full Chip Timing Modeling and Integration Engineer

Altera • San Jose (CA)

Presencial
USD 133.000 - 193.000
Full Chip Timing Modeling and Integration Engineer
Full Chip Timing Modeling and Integration Engineer

191 Altera Corporation • San Jose (CA)

Presencial
USD 133.000 - 193.000
Field Applications Engineer (FAE)
Field Applications Engineer (FAE)

191 Altera Corporation • San Jose (CA)

Presencial
USD 187.000 - 271.000
Senior Lead Design Engineer
Senior Lead Design Engineer

Altera Corporation • San Jose (CA)

Presencial
USD 232.000 - 330.000