Senior Physical Design Engineer — FPGA & SoC Innovation

Altera Corporation; San Jose (CA); On-site; USD 133,000 - 193,000; Full time

Job summary

Altera Corporation in San Jose, CA, invites a Senior Physical Design Engineer to lead physical implementation of IP and SoC designs from RTL to GDSII, driving timing closure, power optimization, and signoff for next-generation FPGA products.

You will collaborate with RTL, DFT, timing, and CAD teams to deliver high-quality silicon, apply advanced PPA techniques, and continuously improve design flows and automation.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline.
• 6+ years hands-on experience with digital ASIC or SoC physical design implementation.
• 6+ years RTL-to-GDSII physical design flows.
• 6+ years synthesis, floorplanning, place and route, and CTS.
• 4+ years physical verification including DRC/LVS/ERC and signoff.
• 4+ years using industry-standard PD EDA tools (Fusion Compiler, ICC2, PrimeTime, Innovus).
• 3+ years optimizing for power, performance, and area (PPA).
• 2+ years supporting designs with multiple voltage/power domains.

Responsibilities

• Perform physical design implementation from RTL through GDSII to manufacturing-ready database.
• Execute synthesis, floorplanning, place and route, CTS, STA, and power/clock distribution.
• Perform physical verification and signoff (EC, STA, reliability, PCI, ERC, layout checks).
• Analyze results, identify violations, and develop solutions for current and future architectures.
• Apply expertise in PD clock design, timing closure, placement, routing, DFT, multi‑power domain analysis.
• Optimize PD to improve power, performance, frequency, and area (PPA).
• Collaborate with RTL, CAD, Timing, DFT, and verification teams to resolve challenges.
• Contribute to PD methodologies, flows, and automation.

Skills

Digital ASIC/SoC

RTL-to-GDSII flow

Timing closure

Power optimization

DFT integration

Multi‑domain design

Collaboration

Problem solving

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Tools

Synopsys Fusion Compiler

ICC2

PrimeTime

Cadence Innovus

Job description

Altera Corporation in San Jose, CA, invites a Senior Physical Design Engineer to lead physical implementation of IP and SoC designs from RTL to GDSII, driving timing closure, power optimization, and signoff for next-generation FPGA products.

You will collaborate with RTL, DFT, timing, and CAD teams to deliver high-quality silicon, apply advanced PPA techniques, and continuously improve design flows and automation.