Senior DFT/ATPG Engineer - SoC & Memory

Katalyst-Healthcares-; Santa Clara (CA); On-site; USD 140,000 - 220,000; Full time

Job summary

Katalyst-Healthcares- in Santa Clara, CA, seeks an experienced Design for Test (DFT) and ATPG engineer to support advanced SoC/ASIC programs. The role emphasizes hands-on DFT/ATPG development, pattern generation, analysis, and debugging across complex semiconductor projects.

You will work with MBIST architectures, I/O test methodologies, clock DFT concepts, and RTL fundamentals while collaborating in a fast-paced, high-performance team environment.

Qualifications

• 5+ years hands-on experience in Design for Test (DFT) and ATPG for SoC or ASIC designs.
• Strong understanding of DFT fundamentals (controllability, observability, scan-based testing).
• Expertise in ATPG pattern generation, analysis, and debugging.
• Experience with MBIST, memory test architectures and diagnostics.
• Knowledge of I/O test methodologies for interface- and pin-level validation.
• Solid understanding of clock DFT and clock verification concepts.
• Strong knowledge of digital design and RTL fundamentals.
• Experience with industry-standard DFT/ATPG EDA tools.
• Ability to work in fast-paced, high-performance semiconductor programs.
• Strong analytical, problem-solving, and communication skills.

Skills

DFT design

ATPG

MBIST

I/O testing

Clock DFT

RTL fundamentals

EDA tools

fast-paced semiconductor programs

Analytical skills

Communication

Job description

Katalyst-Healthcares- in Santa Clara, CA, seeks an experienced Design for Test (DFT) and ATPG engineer to support advanced SoC/ASIC programs. The role emphasizes hands-on DFT/ATPG development, pattern generation, analysis, and debugging across complex semiconductor projects.

You will work with MBIST architectures, I/O test methodologies, clock DFT concepts, and RTL fundamentals while collaborating in a fast-paced, high-performance team environment.