Senior DFT Engineer - ASIC/SoC ATPG & MBIST

ZScale LLC; Santa Clara (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

ZScale LLC is seeking an experienced DFT engineer to design, validate, and optimize scan insertion, ATPG, and test architectures for advanced ASIC/SoC projects in California. The role collaborates with RTL, physical design, and test teams to ensure robust DFT integration and manufacturing readiness.

The candidate will debug RTL, gate-level, and post-layout DFT issues, implement automation scripts, and drive sign-off with a focus on test time reduction and silicon reliability.

Qualifications

• DFT design experience for complex ASIC/SoC.
• Experience with ATPG/MBIST architectures and test modes.

Responsibilities

• Perform Scan Insertion, ATPG generation, and DFT implementation for complex ASIC/SoC designs.
• Develop and validate DFT architecture, scan structures, compression logic, and test modes.
• Execute ATPG validation, fault coverage analysis, and pattern debugging.
• Collaborate with RTL, physical design, and test teams for seamless DFT integration.
• Debug DFT issues at RTL, netlist, and post-layout stages; drive root-cause fixes.
• Optimize DFT flows for reduced test time and improved coverage.
• Support silicon bring-up, test program development, and production test readiness.
• Adhere to DFT best practices, methodologies, and project quality standards.
• Develop and maintain DFT scripts (Tcl, Python, Shell).
• Perform DFT sign-off ensuring coverage targets and manufacturing guidelines.
• Integrate MBIST/LBIST structures and validate memory test algorithms.
• Analyze fault coverage reports and drive improvements in testability.
• Work with silicon test teams to support ATE pattern bring-up and debug failures.
• Validate DFT logic at RTL, gate-level, and post-layout using simulation and formal techniques.
• Ensure JTAG/Boundary Scan (IEEE 1149.1/1500) compliance for board-level testing.

Skills

DFT

ATPG

MBIST/LBIST

JTAG/Boundary Scan

Scripting (Tcl)

Scripting (Python)

Scan Insertion

ASIC/SoC validation

Tools

Mentor Tessent (Siemens)

Synopsys DFT Compiler

Job description

ZScale LLC is seeking an experienced DFT engineer to design, validate, and optimize scan insertion, ATPG, and test architectures for advanced ASIC/SoC projects in California. The role collaborates with RTL, physical design, and test teams to ensure robust DFT integration and manufacturing readiness.

The candidate will debug RTL, gate-level, and post-layout DFT issues, implement automation scripts, and drive sign-off with a focus on test time reduction and silicon reliability.