Senior DFT & ATPG Engineer for SoC/ASIC

Apetan Consulting LLC; Santa Clara (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Apetan Consulting LLC in Santa Clara, CA is seeking a senior DFT/ATPG engineer to drive test solution design for complex SoC/ASIC projects.

You will implement ATPG patterns, analyze failures, and collaborate with RTL teams to improve controllability and observability.

Applicants should have 5+ years hands-on experience and strong debugging skills in fast-paced semiconductor programs.

Qualifications

• 5+ years hands-on experience in DFT/ATPG for SoC/ASIC
• Strong understanding of controllability & observability
• Experience with MBIST and memory test architectures
• Knowledge of IO test validation and clock DFT concepts

Skills

DFT fundamentals

Scan-based testing

ATPG pattern generation

ATPG analysis & debugging

MBIST & memory tests

IO test methodologies

Clock DFT concepts

RTL & digital design

DFT/ATPG EDA tools

Analytical communication skills

Job description

Apetan Consulting LLC in Santa Clara, CA is seeking a senior DFT/ATPG engineer to drive test solution design for complex SoC/ASIC projects.

You will implement ATPG patterns, analyze failures, and collaborate with RTL teams to improve controllability and observability.

Applicants should have 5+ years hands-on experience and strong debugging skills in fast-paced semiconductor programs.