Senior DFT/ATPG Engineer for SoC/ASIC Design

L&T Technology Services; Santa Clara (CA); Sur place; USD 90 000 - 190 000; Plein temps

Avantages offerts par ce poste

Paid Leave

Health Insurance

Group life Insurance

Disability

401(K)

Résumé du poste

L&T Technology Services in California is seeking an experienced DFT/ATPG engineer to contribute to advanced SoC/ASIC verification. This role emphasizes hands-on pattern generation, analysis, and debug across complex semiconductor programs.

The ideal candidate has 5+ years in DFT/ATPG, strong knowledge of MBIST, IO validation, and clock DFT, with a solid background in RTL and digital design. Excellent problem-solving and communication skills are essential.

Qualifications

• 5+ years of hands-on experience in DFT and ATPG for SoC/ASIC designs.
• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing.
• Proven expertise in ATPG pattern generation, analysis, and debug.
• Experience with MBIST, including memory test architectures and diagnostics.

Connaissances

DFT & ATPG

ATPG patterns

MBIST

IO testing

Clock DFT

RTL & digital design

EDA tools

Analytical skills

Communication skills

DFT fundamentals

Outils

DFT/ATPG EDA tools

Description du poste

L&T Technology Services in California is seeking an experienced DFT/ATPG engineer to contribute to advanced SoC/ASIC verification. This role emphasizes hands-on pattern generation, analysis, and debug across complex semiconductor programs.

The ideal candidate has 5+ years in DFT/ATPG, strong knowledge of MBIST, IO validation, and clock DFT, with a solid background in RTL and digital design. Excellent problem-solving and communication skills are essential.