Senior DFT Engineer: SoC/ASIC Test & ATPG Expert

Sira Consulting, an Inc 5000 company; Santa Clara (CA); On-site; USD 120,000 - 210,000; Full time

Job summary

Sira Consulting is seeking an experienced DFT/ATPG engineer to join our fast-paced semiconductor programs in the United States. The role focuses on ATPG pattern generation, memory test architectures, and comprehensive DFT/ATPG validation across SoC/ASIC designs.

The candidate should have strong analytical and communication skills, deep knowledge of DFT fundamentals, and hands-on experience with industry standard DFT/ATPG EDA tools.

Qualifications

• 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs.
• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing.
• Proven expertise in ATPG pattern generation, analysis, and debug.
• Experience with MBIST, including memory test architectures and diagnostics.
• Knowledge of IO Test methodologies for interface and pin level validation.
• Solid understanding of clock DFT and clock verification concepts.
• Strong grasp of digital design and RTL fundamentals.
• Experience with industry standard DFT/ATPG EDA tools.
• Ability to work effectively in fast paced, high performance semiconductor programs.
• Strong analytical, problem solving, and communication skills.

Skills

DFT fundamentals

ATPG pattern generation

analytical skills

problem solving

communication skills

RTL fundamentals

clock DFT

clock verification concepts

digital design

Tools

DFT/ATPG EDA tools

Job description

Sira Consulting is seeking an experienced DFT/ATPG engineer to join our fast-paced semiconductor programs in the United States. The role focuses on ATPG pattern generation, memory test architectures, and comprehensive DFT/ATPG validation across SoC/ASIC designs.

The candidate should have strong analytical and communication skills, deep knowledge of DFT fundamentals, and hands-on experience with industry standard DFT/ATPG EDA tools.