Senior DFT/ATPG Design Engineer for SoC & ASICs

Tiltedge Solutions; Santa Clara (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Tiltedge Solutions in Santa Clara, CA seeks an experienced DFT/ATPG engineer to own test architecture for SoC/ASICs, focusing on controllability, observability, and scan-based testing. You will design and optimize test strategies to ensure high-quality silicon.

The role requires leading ATPG pattern generation, MBIST memory test architectures, and IO test validation, collaborating with RTL and digital design teams in a fast-paced program. Strong analytical and communication skills are essential.

Qualifications

• 5+ years hands-on experience in DFT and ATPG for SoC/ASIC designs.
• Strong understanding of DFT fundamentals: controllability, observability, scan-based testing.
• Expertise in ATPG pattern generation, analysis and debug.
• Experience with MBIST, including memory test architectures and diagnostics.
• Knowledge of IO Test methodologies for interface and pin validation.
• Understanding clock DFT and clock verification concepts.
• Solid understanding of digital design and RTL fundamentals.
• Experience with industry-standard DFT/ATPG EDA tools.
• Ability to work in fast-paced, high performance semiconductor programs.
• Strong analytical, problem solving, and communication skills.

Skills

DFT & ATPG

MBIST

IO Test methods

RTL design

EDA tools

Test pattern debug

Communication

Tools

DFT/ATPG Tools

Job description

Tiltedge Solutions in Santa Clara, CA seeks an experienced DFT/ATPG engineer to own test architecture for SoC/ASICs, focusing on controllability, observability, and scan-based testing. You will design and optimize test strategies to ensure high-quality silicon.

The role requires leading ATPG pattern generation, MBIST memory test architectures, and IO test validation, collaborating with RTL and digital design teams in a fast-paced program. Strong analytical and communication skills are essential.