Senior DFT Engineer for ASIC/SoC Test – Onsite

Select Minds LLC; Lansing (MI); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Day-1 Onsite

Competitive salary

Opportunity for advancement

Job summary

Select Minds LLC in Santa Clara, CA, is seeking a seasoned DFT Engineer to design and implement robust DFT solutions for high‑volume ASIC/SoC devices. You will drive test coverage, fault analysis, and production testing across the development lifecycle.

The role focuses on Scan Compression, MBIST, LBIST, JTAG/IJTAG, and ATPG, with collaboration across Design, Verification, and Physical Design teams. Onsite candidates preferred.

Qualifications

• 5+ years hands‑on experience in Design for Test (DFT).
• Proficient in Scan, MBIST, LBIST, ATPG and JTAG/IJTAG.
• Strong knowledge of IEEE 1149.1/1500/1687 standards.
• Experience with DFT tools from major vendors.

Responsibilities

• Design and implement DFT architectures for ASIC/SoC designs.
• Develop and integrate Scan Compression, MBIST, LBIST, JTAG and IJTAG solutions.
• Perform ATPG, fault simulation, and test coverage analysis.
• Support silicon bring‑up, debug, characterization and production testing.
• Collaborate with Design, Verification and Product Engineering teams.

Skills

DFT

Scan/Compression

MBIST

LBIST

ATPG

JTAG

IJTAG

IEEE 1149.1

IEEE 1500

IEEE 1687

Verilog/SystemVerilog

Python/Perl

Tools

Synopsys TestMAX

DFT Compiler

Siemens Tessent

Cadence Modus

Job description

Select Minds LLC in Santa Clara, CA, is seeking a seasoned DFT Engineer to design and implement robust DFT solutions for high‑volume ASIC/SoC devices. You will drive test coverage, fault analysis, and production testing across the development lifecycle.

The role focuses on Scan Compression, MBIST, LBIST, JTAG/IJTAG, and ATPG, with collaboration across Design, Verification, and Physical Design teams. Onsite candidates preferred.