Senior DFT Engineer for ASIC/SoC Test & Validation

Etched; San Jose (CA); On-site; USD 160,000 - 230,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Housing subsidy of $2k/month

Relocation support

Daily meals provided

Wellness benefits

Job summary

A cutting-edge technology company in San Jose is looking for a highly skilled Design For Testability (DFT) Engineer. This role entails developing DFT architectures for ASIC designs and collaborating with cross-functional teams to ensure robust testing. Candidates should have over 10 years of DFT experience, proficiency in System Verilog, and a Bachelor’s degree in Electrical Engineering. The position offers competitive medical benefits, a housing subsidy, and a dynamic work environment focused on technological advancement.

Qualifications

• 10+ years of experience in DFT engineering with successful test implementations.
• Proficiency in System Verilog and familiarity with EDA tools.
• Strong analytical and debugging skills.

Responsibilities

• Develop and implement DFT architectures for ASIC and SoC designs.
• Collaborate with design and verification teams to address DFT requirements.
• Create comprehensive DFT verification plans.

Skills

DFT engineering

Digital design

System Verilog

Scripting (Python, Perl, TCL)

Debugging skills

Education

Bachelor's in Electrical Engineering

Master's preferred

Tools

Synopsys DFT Compiler

Cadence Encounter Test

Mentor Tessent

Job description

A cutting-edge technology company in San Jose is looking for a highly skilled Design For Testability (DFT) Engineer. This role entails developing DFT architectures for ASIC designs and collaborating with cross-functional teams to ensure robust testing. Candidates should have over 10 years of DFT experience, proficiency in System Verilog, and a Bachelor’s degree in Electrical Engineering. The position offers competitive medical benefits, a housing subsidy, and a dynamic work environment focused on technological advancement.