Associate Design Verification Engineer - UVM SystemVerilog

Millennium Software and Staffing Inc; San Jose (CA); On-site; USD 70,000 - 100,000; Part time

Job summary

A leading staffing and recruiting firm is seeking a Design Verification Engineer in San Jose, California. This role requires skills in UVM, UPF, VIP, System Verilog, VHDL, and SOC verification, with Python or TCL experience beneficial. The position is for contract employment aimed at Associate level candidates working in design-focused management. Ideal for those looking to enhance their expertise in a fast-paced technology environment.

Skills

UVM / UPF / VIP

System Verilog / VHDL

SOC verification

Python

TCL

Job description

A leading staffing and recruiting firm is seeking a Design Verification Engineer in San Jose, California. This role requires skills in UVM, UPF, VIP, System Verilog, VHDL, and SOC verification, with Python or TCL experience beneficial. The position is for contract employment aimed at Associate level candidates working in design-focused management. Ideal for those looking to enhance their expertise in a fast-paced technology environment.