Senior Design Verification Engineer - SoC IP & Silicon

Apple Inc.; Cary (NC); On-site; USD 140,000 - 190,000; Full time

Job summary

Apple Inc. in Cary, North Carolina is seeking an outstanding Design Verification Engineer to help deliver first silicon for IP designs. You will drive pre-silicon verification, develop DV methodology, test plans, and stimulus/testbenches.

You will build SystemVerilog/UVM environments, write tests, fix regressions, and use analytics and LLMs to improve coverage and efficiency. A BS with 10+ years of industry experience is required.

Qualifications

• BS degree with 10+ years of industry experience.
• Deep knowledge of SystemVerilog and UVM.
• Experience with DV methodologies and tools (simulators, waveform viewers, automation, coverage).
• Experience using LLMs for verification efficiency and quality.

Responsibilities

• Study design specification and create test plans.
• Develop infrastructure in SystemVerilog/UVM to stress the design.
• Develop and fix failures from regressions, close bugs.
• Use LLMs to improve verification efficiency and coverage.

Skills

SystemVerilog

UVM

Test Benches

LLMs in verification

Power-aware UPF

Scripting (Python/Perl/TCL)

PCIe/USB DDR

Formal verification (plus)

Emulation technologies (plus)

Verification methodologies

Education

BS degree in electrical/computer engineering

Job description

Apple Inc. in Cary, North Carolina is seeking an outstanding Design Verification Engineer to help deliver first silicon for IP designs. You will drive pre-silicon verification, develop DV methodology, test plans, and stimulus/testbenches.

You will build SystemVerilog/UVM environments, write tests, fix regressions, and use analytics and LLMs to improve coverage and efficiency. A BS with 10+ years of industry experience is required.