SoC Full Chip DV Engineer

Apple Inc.; Austin (TX); On-site; USD 100,000 - 140,000; Full time

Job summary

A leading technology company based in Austin is seeking a Design Verification Engineer to verify the functionality and performance of their premier SOCs. You will work closely with design, architecture, and software teams to ensure quality, developing test plans and methodologies. Ideal candidates have a BS degree, 3+ years of experience in digital verification, and knowledge of Verilog/SystemVerilog. Excellent interpersonal skills are essential. Join a diverse and inclusive workplace fostering equal opportunity.

Qualifications

• Minimum of BS + 3 years relevant industry experience.
• Skilled in many aspects of digital verification.
• Ability to work independently.

Responsibilities

• Verify the functionality and performance of Apple’s SOCs.
• Review design and architecture specifications.
• Develop test plans and coverage plans.

Skills

Digital verification

C/C++

Verilog/SystemVerilog

Python or similar scripting language

Education

BS in relevant field

Job description

Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple’s premier SOCs. This is a critical job within Apple's Hardware Technology, and we'd love to have you join us.

Description

As part of a very talented team, we are at the heart of the chip design effort collaborating with all fields (vertical product model)! You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test effectively. You develop test plans; tests & coverage plans as well as define our next generation verification methodology & test benches. It's required that you communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. We also require additional responsibilities such as running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results.

Minimum Qualifications

• Minimum of BS + 3 years relevant industry experience.

Preferred Qualifications

• Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
• Knowledge of Verilog/SystemVerilog, digital simulation and debug
• Knowledge of computer architecture and digital design fundamentals
• Ability to work independently to deliver the project goals
• Exposure to UVM is desired
• Experience with C/C++, assembly is a plus
• Experience with perl, python or similar scripting language
• Excellent interpersonal skills and the dream to take on diverse challenges

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .