Design Verification Engineer — First Silicon & Stock Options

Apple Inc.; Los Angeles (CA); On-site; USD 175,000 - 309,000; Full time

Job summary

Apple Inc. in Los Angeles seeks a design verification engineer to enable bug-free first silicon for IP designs. You will define DV methodologies, develop test plans, and build verification environments with stimulus, checkers, assertions, and coverage trackers.

Responsibilities include stress testing in SystemVerilog/UVM, debugging regressions, and delivering RTL freeze sign-off. The role also explores LLM-assisted verification to improve efficiency and quality.

Qualifications

• BS degree in technical subject area with minimum 10 years of proven experience or equivalent.
• Deep knowledge of OOP, SystemVerilog and UVM.
• Strong experience with verification methodologies and tools (simulators, waveform viewers, automation, coverage).
• Experience with LLMs for efficiency and quality.
• Power-aware (UPF) or similar verification methodology is a plus.
• Scripting languages such as Python, Perl, TCL are a plus.
• Experience with serial protocols such as PCIe or USB is a plus.
• Knowledge of formal verification is a plus.
• Knowledge of emulation for verification technologies is a plus.

Responsibilities

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions, close bugs
• Use LLMs to do verification efficiently

Skills

SystemVerilog

UVM

OOP

LLMs

UPF

Python

Perl

TCL

PCIe

USB

Formal verification

Emulation

Education

BS degree in technical subject area

Tools

Simulators

Waveform viewers

Build/run automation

Coverage

Gate-level simulations

Job description

Apple Inc. in Los Angeles seeks a design verification engineer to enable bug-free first silicon for IP designs. You will define DV methodologies, develop test plans, and build verification environments with stimulus, checkers, assertions, and coverage trackers.

Responsibilities include stress testing in SystemVerilog/UVM, debugging regressions, and delivering RTL freeze sign-off. The role also explores LLM-assisted verification to improve efficiency and quality.