Silicon Design Verification Lead – Lead High-Impact Teams

Apple Inc.; Austin (TX); On-site; USD 300,000 - 380,000; Full time

Job summary

Apple Inc. seeks a Senior Engineering Leader in Silicon Design Verification to guide one or more verification teams developing cutting‑edge silicon IPs. You will provide technical leadership, drive best practices, and ensure first‑pass success across performance, power, and area targets.

As a hands‑on leader you will mentor engineers, collaborate with architecture, design and software teams to define verification requirements, drive strategy, and implement test plans using SystemVerilog and UVM.

Qualifications

• BS and a minimum of 20 years relevant industry experience.
• Experience leading verification teams.
• Strong SystemVerilog and UVM expertise.
• Knowledge of UPF low-power verification and power intent validation.
• Background in high-speed interfaces (PCIe, USB, DDR) and multi-site leadership.

Responsibilities

• Lead, grow and mentor a team of verification engineers, providing technical guidance and performance assessment.
• Define verification requirements, drive strategy, planning, environment implementation and methodology.
• Develop and execute functional and power-aware verification plans, focusing on test coverage, formal verification, and assertion-based verification.
• Collaborate with architecture, design and software teams to ensure first-pass success of silicon designs.

Skills

SystemVerilog

UVM

Leadership

Verification strategy

Testbench development

Debugging

Cross-functional collaboration

Power/Performance awareness

Education

Bachelor's degree in Electrical Engineering or related

Tools

UPF methodology

Emulation

Formal verification

Job description

Apple Inc. seeks a Senior Engineering Leader in Silicon Design Verification to guide one or more verification teams developing cutting‑edge silicon IPs. You will provide technical leadership, drive best practices, and ensure first‑pass success across performance, power, and area targets.

As a hands‑on leader you will mentor engineers, collaborate with architecture, design and software teams to define verification requirements, drive strategy, and implement test plans using SystemVerilog and UVM.