Senior Design Verification Engineer – SoC/IP (Pre-silicon)

Apple Inc.; United States; On-site; USD 185,000 - 325,000; Full time

Job summary

Apple Inc. in the San Francisco Bay Area is seeking a design verification engineer to enable first silicon for IP designs. You will develop DV environments, create test plans, and drive bug fixes across pre-silicon verification stages.

Ideal candidates have deep SystemVerilog/UVM knowledge, scalable test-benches, and experience with verification tooling; familiarity with UPF and scripting languages is a plus. This role emphasizes innovation and collaboration.

Qualifications

• Deep knowledge of SystemVerilog/UVM and verification methodologies.
• Experience building scalable, portable test-benches.
• Proficiency with simulators, waveform viewers, automation, coverage, and gate-level sims.
• Experience using LLMs to improve verification efficiency and quality.
• Knowledge of UPF or similar power-aware verification.

Responsibilities

• Study design specification and create test plans for IP/SoC blocks.
• Develop and fix failures from regressions; drive bug closure.
• Develop verification environments and DV infrastructure using SystemVerilog/UVM.
• Apply LLMs to optimize verification workflows and results.

Skills

SystemVerilog

UVM

OOP concepts

Testbenches

LLMs in verification

UPF

Python

Perl

TCL

PCIe

USB

DDR

Emulation

Formal verification

Education

BS degree in technical subject area

Job description

Apple Inc. in the San Francisco Bay Area is seeking a design verification engineer to enable first silicon for IP designs. You will develop DV environments, create test plans, and drive bug fixes across pre-silicon verification stages.

Ideal candidates have deep SystemVerilog/UVM knowledge, scalable test-benches, and experience with verification tooling; familiarity with UPF and scripting languages is a plus. This role emphasizes innovation and collaboration.