Design Verification Engineer — SOC & IP Architect

Apple Inc.; Sunnyvale (CA); On-site; USD 150,400 - 277,600; Full time

Benefits offered by this job

Medical and dental coverage

Stock plan eligibility

Relocation assistance

Education reimbursement

Job summary

Apple is seeking a Design Verification Engineer in Cupertino, CA to verify functionality and performance of Apple’s SOCs. You will develop test plans, coverage, and testbenches while collaborating with design, architecture and software teams.

You’ll work across IPs and subsystems, ranging from Neural Engine hardware to high-speed I/O and memory subsystems, contributing to next-generation verification methodologies.

Qualifications

• BS degree plus 3 years of relevant industry experience.
• Experience with SystemVerilog, digital simulation, and debugging.
• Knowledge of computer architecture and digital design fundamentals.
• SW programming skills with data structures and algorithms.
• Experience with Python, Perl, or similar scripting language.
• Familiarity with verification methodologies like UVM.
• C/C++, assembly is a plus.
• Excellent interpersonal skills and a passion for tackling diverse challenges.

Responsibilities

• Verify functionality and performance of Apple’s premier SOCs.
• Develop test plans, tests, and coverage plans for verification.
• Define our verification methodology and testbenches.
• Communicate and collaborate with design, architecture and software teams.
• Drive test cases and understand use cases and corner conditions.
• Work on IPs or subsystems such as Neural Engine, PCIe, DisplayPort, and memory subsystems.

Skills

SystemVerilog

Digital verification

Python

C/C++

Debugging

Computer architecture

Algorithms

UVM

Assembly

Education

BS degree + 3 years experience

Job description

Apple is seeking a Design Verification Engineer in Cupertino, CA to verify functionality and performance of Apple’s SOCs. You will develop test plans, coverage, and testbenches while collaborating with design, architecture and software teams.

You’ll work across IPs and subsystems, ranging from Neural Engine hardware to high-speed I/O and memory subsystems, contributing to next-generation verification methodologies.