Senior Design Verification Engineer (SoC)

Apple Inc.; California; On-site; USD 172,000 - 302,000; Full time

Benefits offered by this job

Comprehensive medical and dental coverage

Retirement benefits

Discounted products and services

Educational reimbursement

Job summary

A leading technology company in California is seeking a Design Verification Engineer to ensure bug-free silicon for cutting-edge products. The role includes developing test plans, infrastructure in SystemVerilog/UVM, and leveraging LLMs for verification. Candidates should possess a BS degree and a minimum of 10 years of experience. Competitive compensation and extensive benefits are part of the package.

Qualifications

• Minimum 10 years of proven experience in a relevant field.
• Deep knowledge of verification methodologies and tools.
• Experience with power-aware verification methodologies is a plus.

Responsibilities

• Study design specifications and create test plans.
• Develop infrastructure in SystemVerilog/UVM to stress designs.
• Develop and fix failures from regressions, close bugs.

Skills

Design specification analysis

SystemVerilog

UVM

Use of LLMs in verification

Debugging

Education

BS degree in technical subject area

Tools

Simulation tools

Coverage collection tools

Scripting languages (Python, Perl, TCL)

Job description

A leading technology company in California is seeking a Design Verification Engineer to ensure bug-free silicon for cutting-edge products. The role includes developing test plans, infrastructure in SystemVerilog/UVM, and leveraging LLMs for verification. Candidates should possess a BS degree and a minimum of 10 years of experience. Competitive compensation and extensive benefits are part of the package.