Senior SoC Verification Engineer

Capgemini Engineering; Santa Clara (CA); On-site; USD 97,700 - 182,624; Full time

Benefits offered by this job

Healthcare including dental and vision

401(k) plan

Paid parental leave

Paid time off

Social well-being benefits

Job summary

A leading engineering firm in Santa Clara is looking for a Design Verification Engineer to join their team. In this role, you will validate advanced System-on-Chip designs and work closely with architects and design engineers. The ideal candidate will have extensive experience with SystemVerilog, UVM, and a proactive approach to problem-solving. Competitive compensation and comprehensive benefits are offered.

Qualifications

• 7+ years of experience in pre-silicon design verification.
• Hands-on experience verifying SoCs with ARM Cortex microcontrollers.
• Familiarity with timing analysis.

Responsibilities

• Architect and implement scalable verification environments using SystemVerilog and UVM.
• Develop test plans and execute verification at both block and chip levels.
• Drive continuous improvement by identifying verification gaps.

Skills

SystemVerilog

UVM

Python

C-shell scripting

Verification methodologies

Analytical skills

Problem-solving skills

Education

Bachelor’s degree in Electrical Engineering or equivalent

Tools

Synopsys EDA tools

Cadence EDA tools

Job description

A leading engineering firm in Santa Clara is looking for a Design Verification Engineer to join their team. In this role, you will validate advanced System-on-Chip designs and work closely with architects and design engineers. The ideal candidate will have extensive experience with SystemVerilog, UVM, and a proactive approach to problem-solving. Competitive compensation and comprehensive benefits are offered.