Senior Verification Engineer – UVM, SoC Memory & PCIe

Tara Technical Solutions (TTS); San Jose (CA); On-site; USD 130,000 - 192,000; Full time

Benefits offered by this job

Medical insurance

Vision insurance

401(k)

Paid maternity leave

Child care support

Pension plan

Paid paternity leave

Student loan assistance

Disability insurance

Tuition assistance

Job summary

A leading semiconductor firm in San Jose is seeking a Design Verification Engineer responsible for verifying complex designs. The ideal candidate will have significant experience designing test benches and a strong grasp of verification methodologies like UVM. A Bachelor's degree with relevant experience is required. Competitive salary and benefits are offered, including health insurance and 401(k).

Qualifications

• Expertise in architecting reusable and constrained random test benches from scratch.
• Strong understanding of System Verilog assertions.

Responsibilities

• Responsible for verification from test planning to functional/code coverage closure.
• Conduct verification on complex designs and IP interfaces.

Skills

Expertise in architecting reusable and constrained random test benches

Expertise in verification methodologies like UVM

Verification expertise with Interface IP designs

Experience with ARM based bus protocols

Strong understanding of System Verilog assertions

Education

Bachelor's Degree + 8+ years of experience

Master's Degree + 6+ years of experience

Job description

A leading semiconductor firm in San Jose is seeking a Design Verification Engineer responsible for verifying complex designs. The ideal candidate will have significant experience designing test benches and a strong grasp of verification methodologies like UVM. A Bachelor's degree with relevant experience is required. Competitive salary and benefits are offered, including health insurance and 401(k).