Design Verification Engineer – Systolic Arrays & NoCs

Etched; San Jose (CA); On-site; USD 150,000 - 275,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 monthly medical benefits credit

Housing subsidy of $2k per month

Relocation support for moving to San Jose

Various wellness benefits

Daily lunch + dinner in office

Job summary

A cutting-edge technology company in San Jose is seeking a Design Verification Engineer. The role demands expertise in UVM and SystemVerilog to ensure custom IPs are robust and silicon-ready. You will tackle complex verification challenges, collaborating closely with teams to validate performance across the hardware-software stack. The company offers generous benefits including medical coverage, housing subsidies, and daily meals, along with a competitive compensation range of $150K - $275K.

Qualifications

• Proficient in UVM and SystemVerilog for design verification.
• Strong problem-solving skills for complex digital designs.
• Hands-on experience verifying datapaths and memory systems.

Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches.
• Define and execute verification plans covering functional correctness.
• Debug complex datapath and protocol issues.

Skills

Proficiency with UVM

Strong debugging skills

Solid knowledge of computer architecture

Tools

SystemVerilog

Python

TCL

Job description

A cutting-edge technology company in San Jose is seeking a Design Verification Engineer. The role demands expertise in UVM and SystemVerilog to ensure custom IPs are robust and silicon-ready. You will tackle complex verification challenges, collaborating closely with teams to validate performance across the hardware-software stack. The company offers generous benefits including medical coverage, housing subsidies, and daily meals, along with a competitive compensation range of $150K - $275K.