A leading technology company located in Cupertino is seeking a Design Verification Engineer who will be responsible for verifying the functionality and performance of SOCs. The role involves collaboration across various teams to ensure the highest quality in chip design, requiring knowledge of digital design fundamentals and programming languages. With a base pay range of $126,800 to $190,900, the position also offers comprehensive benefits including medical coverage, stock programs, and educational reimbursements.
Qualifications
Proven understanding of computer architecture and digital design fundamentals.
Familiarity with verification languages and programming.
Ability to work independently and deliver project goals.
Responsibilities
Verify functionality and performance of SOCs.
Collaborate with design and micro-architecture teams.
Develop test plans and methodologies.
Skills
Knowledge of computer architecture and digital design fundamentals
Knowledge of Verilog or SystemVerilog
Experience with Python, Perl, or similar scripting language
Experience with C/C++ or assembly
Excellent interpersonal skills
Education
BS in a relevant field
Job description
A leading technology company located in Cupertino is seeking a Design Verification Engineer who will be responsible for verifying the functionality and performance of SOCs. The role involves collaboration across various teams to ensure the highest quality in chip design, requiring knowledge of digital design fundamentals and programming languages. With a base pay range of $126,800 to $190,900, the position also offers comprehensive benefits including medical coverage, stock programs, and educational reimbursements.