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Job summary
A semiconductor design company based in Chicago is seeking a Design Verification Engineer to ensure the functional correctness and reliability of complex semiconductor designs. Responsibilities include developing verification plans, building verification environments using SystemVerilog/UVM, and performing RTL debugging. The ideal candidate holds a relevant degree and has strong digital design understanding, UVM experience, and familiarity with simulation tools. This role plays a critical part in ensuring product readiness and quality before tape-out.
Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering or related field.
Strong understanding of digital design and computer architecture.
Hands-on experience with UVM.
Responsibilities
Develop and execute functional verification plans for ASIC/SoC designs.
Bachelor’s or Master’s degree in Electrical Engineering
Tools
VCS
Questa
Xcelium
Job description
A semiconductor design company based in Chicago is seeking a Design Verification Engineer to ensure the functional correctness and reliability of complex semiconductor designs. Responsibilities include developing verification plans, building verification environments using SystemVerilog/UVM, and performing RTL debugging. The ideal candidate holds a relevant degree and has strong digital design understanding, UVM experience, and familiarity with simulation tools. This role plays a critical part in ensuring product readiness and quality before tape-out.