Senior Design Verification Engineer, Networking SoC

AMD; Santa Clara (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

AMD is seeking a skilled Design Verification Engineer in Santa Clara, CA, to drive verification closure on complex ASIC designs. The role requires hands-on verification expertise and strong debugging skills across architecture and RTL.

The ideal candidate will develop UVM-based testbench architectures, manage execution of verification plans, and collaborate cross-functionally to ensure quality deliverables. Rewards include a collaborative culture and opportunities for professional growth.

Qualifications

• Expert-level knowledge of SystemVerilog and UVM.
• Strong hands-on experience with SystemVerilog simulators (VCS preferred).
• Proven experience in verifying complex IP/subsystems.

Responsibilities

• Develop robust UVM-based testbench architectures.
• Drive test plan creation and coverage strategy.
• Own execution of verification plans and debug issues.

Skills

SystemVerilog

UVM

Debugging skills

Python scripting

Familiarity with PCIe, AXI

Education

Bachelor’s Degree in Electrical/Computer Engineering

Master’s Preferred

Tools

VCS

Verdi/DVE

Job description

AMD is seeking a skilled Design Verification Engineer in Santa Clara, CA, to drive verification closure on complex ASIC designs. The role requires hands-on verification expertise and strong debugging skills across architecture and RTL.

The ideal candidate will develop UVM-based testbench architectures, manage execution of verification plans, and collaborate cross-functionally to ensure quality deliverables. Rewards include a collaborative culture and opportunities for professional growth.