Senior Network SoC Verification Engineer

Advanced Micro Devices, Inc.; Santa Clara (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Advanced Micro Devices, Inc. (AMD) is seeking a Design Verification Engineer in Santa Clara to drive verification closure for high‑performance ASIC designs.

You will develop UVM‑based testbenches, create verification plans, and coordinate with RTL, architecture, and firmware teams in a fast‑paced environment. The role emphasizes hands‑on verification, debugging complex RTL issues, and leadership across IP, subsystem, and SoC levels, contributing to AMD networking products and data‑center

Qualifications

• Strong SystemVerilog and UVM expertise.
• Experience with verification of complex IP/subsystems and SoC‑level verification.
• Hands‑on verification, debugging architecture/RTL issues, and cross‑team leadership.

Responsibilities

• Develop robust UVM‑based testbench architectures for IP, subsystem, and SoC‑level verification.
• Drive test plans, feature mapping, and coverage strategy for networking/data‑path IP.
• Own execution of verification plans, regression triage, and debug of RTL/testbench issues.
• Mentor junior DV engineers and collaborate with RTL, architecture, firmware teams.

Skills

SystemVerilog

UVM

RTL debugging

Testbench development

Python scripting

Education

Bachelor's in Electrical/Computer Engineering

Tools

VCS

Verdi/DVE

BFMs/transactors

Job description

Advanced Micro Devices, Inc. (AMD) is seeking a Design Verification Engineer in Santa Clara to drive verification closure for high‑performance ASIC designs.

You will develop UVM‑based testbenches, create verification plans, and coordinate with RTL, architecture, and firmware teams in a fast‑paced environment. The role emphasizes hands‑on verification, debugging complex RTL issues, and leadership across IP, subsystem, and SoC levels, contributing to AMD networking products and data‑center