Design Verification Architect – Networking SoC

AMD; Santa Clara (CA); Sur place; USD 110 000 - 150 000; Plein temps

Résumé du poste

AMD in Santa Clara is seeking a Design Verification Engineer to contribute to advanced data center networking technology. The ideal candidate should have strong expertise in SystemVerilog and UVM, with a focus on complex ASIC designs. Responsibilities include developing testbench architectures and ensuring verification closure on next-generation AMD products.

Join a fast-paced collaborative environment and drive innovation in data center solutions. A Bachelor’s Degree in Electrical/Computer Engineering is required, with a Master’s degree preferred.

Qualifications

• Expert level knowledge of SystemVerilog and UVM required.
• Strong debug skills across architecture, RTL, and testbench layers.
• Proven experience in verifying complex IP with constraints.

Responsabilités

• Develop robust UVM-based testbench architectures.
• Own execution of verification plans and debug issues.
• Collaborate with RTL design, validation, and firmware teams.

Connaissances

Expert knowledge of SystemVerilog

Hands-on experience with VCS

Experience with PCIe, Ethernet

Debug skills across architecture and RTL

Scripting in Python

Formation

Bachelor’s Degree in Electrical/Computer Engineering

Outils

VCS

Verdi/DVE

Python

Description du poste

AMD in Santa Clara is seeking a Design Verification Engineer to contribute to advanced data center networking technology. The ideal candidate should have strong expertise in SystemVerilog and UVM, with a focus on complex ASIC designs. Responsibilities include developing testbench architectures and ensuring verification closure on next-generation AMD products.

Join a fast-paced collaborative environment and drive innovation in data center solutions. A Bachelor’s Degree in Electrical/Computer Engineering is required, with a Master’s degree preferred.