Next-Gen CPU Verification Engineer

Advanced Micro Devices, Inc.; Santa Clara (CA); On-site; USD 140,000 - 180,000; Full time

Job summary

Advanced Micro Devices, Inc. in Santa Clara, CA is seeking a collaborative verification engineer to design verification plans for next-gen CPUs. You will analyze RTL designs, create tests, and drive verification closure across teams.

The role emphasizes SystemVerilog/UVM, C/C++, and robust debugging of complex designs, with opportunities to shape verification environments, coverage strategies, and collaboration with design, testbench, and emulation teams.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering, Computer Engineering, Computer Science or related field preferred.
• Strong knowledge of CPU verification and modern verification methodologies.
• Experience with RTL analysis, debugging and verification planning.

Responsibilities

• Develop verification plans for new CPU features and microarchitectures.
• Analyze RTL designs to understand functionality and verification needs.
• Create and maintain functional and performance tests.
• Develop, enhance, and debug verification environments and testbenches.
• Drive verification areas from planning through closure.
• Conduct coverage analysis and address verification gaps.
• Diagnose complex design/verification issues and resolve them.
• Collaborate with CPU design, verification, testbench, and emulation teams.
• Improve verification methodologies and engineering workflows.
• Provide technical guidance to partner teams.

Skills

CPU verification

SystemVerilog

C/C++

Verification methodologies

Testbench development

Hardware emulation

Formal verification

AI in engineering

Education

Bachelor’s degree in Electrical/Computer Engineering or Computer Science

Tools

SystemVerilog

UVM

C/C++

Job description

Advanced Micro Devices, Inc. in Santa Clara, CA is seeking a collaborative verification engineer to design verification plans for next-gen CPUs. You will analyze RTL designs, create tests, and drive verification closure across teams.

The role emphasizes SystemVerilog/UVM, C/C++, and robust debugging of complex designs, with opportunities to shape verification environments, coverage strategies, and collaboration with design, testbench, and emulation teams.