Lead Design Verification Engineer - Networking ASICs

Advanced Micro Devices; Santa Clara, Northern (CA, KY); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Advanced Micro Devices (AMD) seeks a high-impact Design Verification Engineer to verify high-performance ASICs in a fast-paced, collaborative environment. You will design robust UVM-based testbenches for IP, subsystem, and SoC verification, owning test plans, coverage, and regression closure.

You will mentor junior engineers, drive cross-team verification tasks, and engage with RTL design, architecture, validation, firmware, and emulation teams to deliver high-quality silicon.

Qualifications

• Expert-level SystemVerilog and UVM for ASIC verification.
• Proven experience with test plans, coverage, and constrained-random methodologies.
• Strong debugging across architecture, RTL, and testbench layers.

Responsibilities

• Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
• Own execution of verification plans, regression triage, and debug of issues across RTL and testbench.
• Collaborate with RTL design, architecture, validation, firmware, and emulation teams to ensure quality deliverables.

Skills

SystemVerilog

UVM

VCS

Verdi/DVE

Python

Debugging

Testbench development

Education

Bachelor's in Electrical/Computer Engineering

Tools

VCS

Verdi/DVE

Python

Make

Job description

Advanced Micro Devices (AMD) seeks a high-impact Design Verification Engineer to verify high-performance ASICs in a fast-paced, collaborative environment. You will design robust UVM-based testbenches for IP, subsystem, and SoC verification, owning test plans, coverage, and regression closure.

You will mentor junior engineers, drive cross-team verification tasks, and engage with RTL design, architecture, validation, firmware, and emulation teams to deliver high-quality silicon.