Sr. Design Verification Engineer

Advanced Micro Devices; Santa Clara, Northern (CA, KY); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Advanced Micro Devices (AMD) seeks a high-impact Design Verification Engineer to verify high-performance ASICs in a fast-paced, collaborative environment. You will design robust UVM-based testbenches for IP, subsystem, and SoC verification, owning test plans, coverage, and regression closure.

You will mentor junior engineers, drive cross-team verification tasks, and engage with RTL design, architecture, validation, firmware, and emulation teams to deliver high-quality silicon.

Qualifications

• Expert-level SystemVerilog and UVM for ASIC verification.
• Proven experience with test plans, coverage, and constrained-random methodologies.
• Strong debugging across architecture, RTL, and testbench layers.

Responsibilities

• Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
• Own execution of verification plans, regression triage, and debug of issues across RTL and testbench.
• Collaborate with RTL design, architecture, validation, firmware, and emulation teams to ensure quality deliverables.

Skills

SystemVerilog

UVM

VCS

Verdi/DVE

Python

Debugging

Testbench development

Education

Bachelor's in Electrical/Computer Engineering

Tools

VCS

Verdi/DVE

Python

Make

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

THE ROLE:

AMD's Network Technologies Solutions Group (NTSG) is a leading provider of advanced data center networking technology. Our distributed services platform expands AMD's data center product portfolio with a high-performance DPU and software stack deployed at scale across major cloud and enterprise environments, including Goldman Sachs, IBM Cloud, Microsoft Azure, and Oracle.

THE PERSON:

We are seeking a high-impact Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high-performance ASIC designs.

The ideal candidate brings hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.

You will work in a fast-paced, highly collaborative environment and contribute directly to the success of next‑generation AMD networking products.

KEY RESPONSIBILITIES:

Verification Architecture & Testbench Development

• Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
• Drive test plan creation, feature mapping, and coverage strategy for complex networking and data-path IP.
• Develop high-quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.

Execution, Debug & Closure

• Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
• Root-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.
• Optimize simulations, coverage closure, and verification sign-off methodology.

Tools & Methodology

• Use industry-standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).
• Contribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).

Cross-Functional Collaboration

• Collaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high-quality deliverables.
• Participate in design reviews, micro-architecture definition, and bring a verification perspective into early design stages.
• Mentor junior engineers and provide technical leadership within the verification team.

LANGUAGES & TOOLS

Required

• Expert-level knowledge of SystemVerilog and UVM
• Strong hands-on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)
• Proven experience in verifying complex IP/subsystems with test plans, coverage, and constrained-random methodologies
• Strong debug skills across architecture, RTL, and testbench layers
• Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data-path components
• Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure

Preferred

• Experience with performance verification, power-aware verification (UPF), or formal verification
• Familiarity with FPGA/HAPS-based validation and acceleration flowsUnderstanding of networking or high-speed I/O pipelinesExposure to architectural modeling or C/C++ reference models

PREFERRED QUALIFICATIONS:

• Strong analytical and problem-solving abilities with a proven track record of debugging complex issues
• Ability to lead verification tasks independently and drive cross-team closure
• Excellent verbal and written communication skills
• Comfortable working in a fast-paced, collaborative, multi-site environment
• Ability to mentor and guide junior DV engineers

ACADEMIC CREDENTIALS

Bachelor's Degree in Electrical/Computer Engineering or related field, Master's Preferred

LOCATION:

Hybrid in Santa Clara, CA or Austin, TX

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age