Lead Verification Architect – DDR6 & Memory Interfaces

Renesas Electronics Corporation; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Renesas Electronics Corporation seeks a Principal Design Verification Engineer to lead verification for next‑generation DDR6 memory interface products. You will own verification strategy at block and system levels, architect SystemVerilog/UVM testbenches, and drive coverage closure with RTL teams for high‑assurance designs.

You will mentor verification engineers, shape verification plans, and communicate risks and progress to leadership.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Extensive semiconductor verification experience with ownership of complex verification efforts.
• Expert-level proficiency with SystemVerilog.
• Significant hands-on experience with UVM and verification environments.
• Experience defining verification strategies and developing verification plans from design specs.
• Strong experience with functional verification, constrained-random testing, coverage, and debugging.
• Experience partnering with RTL/design teams throughout the lifecycle.
• Proven ability to independently solve complex verification and design problems.
• Ability to provide technical leadership and mentoring.

Responsibilities

• Lead verification strategy and execution for complex designs at block and system level.
• Define verification methodologies, test plans, coverage strategies, and verification environments.
• Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and verification environments.
• Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure.
• Take ownership of verification for assigned blocks, features, and environments from planning through signoff.
• Collaborate with RTL/design engineers to ensure designs are verifiable and meet requirements.
• Analyze specifications, design, and verification results to identify gaps and issues.
• Lead debugging and resolution of complex verification failures.
• Develop scalable and reusable verification components and best practices.
• Identify and lead improvements in verification efficiency, quality, and reuse.
• Participate in architecture reviews and provide mentorship to engineers.

Skills

SystemVerilog

UVM

Technical leadership

Mentoring

Debug complex verification

Education

Bachelor's or Master's in Electrical/Computer Engineering or related

Tools

UVM environments

Job description

Renesas Electronics Corporation seeks a Principal Design Verification Engineer to lead verification for next‑generation DDR6 memory interface products. You will own verification strategy at block and system levels, architect SystemVerilog/UVM testbenches, and drive coverage closure with RTL teams for high‑assurance designs.

You will mentor verification engineers, shape verification plans, and communicate risks and progress to leadership.