Senior CPU RTL Design Lead (Hybrid)

Intel; Austin (TX); Hybrid; USD 142,000 - 269,000; Full time

Job summary

Intel in Austin is seeking a CPU Logic Design Engineer to design and optimize RTL for next-generation processors. You will drive RTL coding, simulation, and integration of CPU IP blocks across full-chip designs, shaping architecture and microarchitecture features for high performance and energy efficiency.

You'll collaborate with architecture, design, and verification teams, review verification plans, and document MAS specifications.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering, or computer science required.
• 5+ years experience in CPU RTL design using SystemVerilog and strong debugging skills.
• Experience with energy-efficient and low-power design methods for high-frequency optimization.

Responsibilities

• Develop and optimize RTL coding and simulation for the CPU.
• Define architecture and microarchitecture features for the CPU design.
• Write RTL and optimize for power, performance, area and timing goals.
• Review verification plans and ensure RTL tests pass.

Skills

SystemVerilog

RTL design

CPU architecture

Scripting languages

Debug & verification

Education

Bachelor's degree in electrical/computer engineering or computer science

Master's degree in the same field

Tools

SystemVerilog tools

UPF

Lint checks

Job description

Intel in Austin is seeking a CPU Logic Design Engineer to design and optimize RTL for next-generation processors. You will drive RTL coding, simulation, and integration of CPU IP blocks across full-chip designs, shaping architecture and microarchitecture features for high performance and energy efficiency.

You'll collaborate with architecture, design, and verification teams, review verification plans, and document MAS specifications.