CPU RTL Design Engineer – Hybrid Work

Intel; Austin (TX); Hybrid; USD 91,000 - 173,000; Full time

Benefits offered by this job

Health benefits

Stock purchase plan

Hybrid work model

Job summary

Intel seeks a CPU Logic Design Engineer to shape next-generation CPUs through RTL design, architecture refinement, and verification. You will collaborate in a cross-functional team to optimize performance, power, and area while ensuring the design meets timing and integration requirements.

The role emphasizes writing high-quality RTL, documenting microarchitectural specifications, and supporting customers with CPU integration into larger SoCs, with a hybrid work model in the United States.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or a relevant STEM field.
• 3+ months of experience in CPU logic design, computer architecture and/or microprocessors, digital design and RTL coding.
• Verilog/SystemVerilog and/or VHDL experience.
• Scripting languages such as Python, Perl, TCL.

Responsibilities

• Develop RTL coding for CPU components, such as cell libraries, functional units, and CPU IP blocks.
• Define architecture and microarchitecture features to optimize performance, power, and area.
• Write RTL and optimize for power, performance, area, and timing while maintaining design integrity.
• Review and refine verification plans and tests to ensure correct implementation of features.
• Resolve failing RTL tests and implement corrective measures to meet design specifications.
• Document MAS specifications for CPU features and ensure alignment with project goals.
• Support SoC customers to enable seamless integration of the CPU block into larger designs.

Skills

CPU Logic Design

Computer Architecture

RTL coding

Verilog/SystemVerilog

Scripting languages

Education

Bachelor's degree in Electrical or Computer Engineering

Job description

Intel seeks a CPU Logic Design Engineer to shape next-generation CPUs through RTL design, architecture refinement, and verification. You will collaborate in a cross-functional team to optimize performance, power, and area while ensuring the design meets timing and integration requirements.

The role emphasizes writing high-quality RTL, documenting microarchitectural specifications, and supporting customers with CPU integration into larger SoCs, with a hybrid work model in the United States.