Lead CPU RTL Design Engineer – Architect Next‑Gen Microprocessors

Intel; Hillsboro (OR); On-site; USD 164,000 - 312,000; Full time

Job summary

Intel in Hillsboro, Oregon is seeking a CPU RTL Logic Design Engineer to help define architecture, develop RTL, and drive timing, power, and area goals for next‑generation CPUs. You will lead design activities, review verification plans, and collaborate with architecture and backend teams to deliver high‑performance IP blocks.

Bring 6+ years in CPU microarchitecture and logic design, 5+ years of technical leadership, and a track record of delivering IP projects.

Qualifications

• 6+ years in CPU silicon development and logic design.
• 5+ years in technical leadership delivering IP projects.
• 6+ years with Timing Closure and Power Convergence.
• Experience with OOO execution and reservation station design.
• Experience on x86 CPU microarchitecture preferred.

Responsibilities

• Collaborates, drives and develops RTL coding and simulation for CPU IP blocks.
• Participates in architecture/microarchitecture feature definition.
• Writes RTL and optimizes for power, performance, area and timing.
• Reviews verification plans and fixes RTL test issues.
• Provides technical leadership to design teams and drives process improvements.
• Works closely with architecture and backend teams toward best-in-class products.
• Helps build a strong, values-based technical organization.

Skills

silicon development

CPU microarchitecture

RTL design

timing closure

leadership

OOO execution

reservation station design

Education

Bachelor's degree in CS/EE

Master's degree in CS/EE

PhD in CS/EE

Job description

Intel in Hillsboro, Oregon is seeking a CPU RTL Logic Design Engineer to help define architecture, develop RTL, and drive timing, power, and area goals for next‑generation CPUs. You will lead design activities, review verification plans, and collaborate with architecture and backend teams to deliver high‑performance IP blocks.

Bring 6+ years in CPU microarchitecture and logic design, 5+ years of technical leadership, and a track record of delivering IP projects.