CPU RTL Design Engineer — Hybrid Work

Intel; Phoenix (AZ); Hybrid; USD 91,000 - 173,000; Full time

Benefits offered by this job

14 paid holidays

3 weeks vacation

Sabbatical every 4 years

Annual bonuses

Employee stock purchase program

Job summary

Intel in the United States is seeking a CPU Logic Design Engineer to contribute to next-generation microarchitecture. You will develop RTL for CPU components, define architecture features, and optimize power, performance, and area while ensuring timing and verification readiness.

Qualifications include a Bachelor's in Electrical or Computer Engineering and hands-on RTL design, Verilog/SystemVerilog, and Python or TCL. The role is hybrid with US locations, including Phoenix, AZ.

Qualifications

• Bachelor’s Degree in Electrical or Computer Engineering or any STEM related degree.
• 3+ months of experience in CPU Logic Design
• Experience in Computer Architecture and / or Microprocessors
• Digital design and /or RTL coding
• Verilog/System Verilog and/or VHDL
• Scripting languages (Python, Perl, TCL)

Responsibilities

• Develop logic design and RTL coding for CPU components (cell libraries, functional units, CPU IP blocks).
• Define architecture and microarchitecture features to optimize CPU performance, power, and area.
• Write RTL and implement strategies to meet power, performance, area, and timing goals.
• Review and refine verification plans and tests for correct design implementation.
• Resolve failing RTL tests and implement corrective measures.
• Document MAS for CPU features and align with project goals.
• Support SoC customers to integrate CPU blocks into larger designs.

Skills

CPU Logic Design

Computer Architecture / Microprocessor

RTL coding

Verilog / SystemVerilog / VHDL

Python / TCL / Perl

Education

Bachelor’s Degree in Electrical or Computer Engineering (or STEM)

Job description

Intel in the United States is seeking a CPU Logic Design Engineer to contribute to next-generation microarchitecture. You will develop RTL for CPU components, define architecture features, and optimize power, performance, and area while ensuring timing and verification readiness.

Qualifications include a Bachelor's in Electrical or Computer Engineering and hands-on RTL design, Verilog/SystemVerilog, and Python or TCL. The role is hybrid with US locations, including Phoenix, AZ.