CPU Verification Architect — SystemVerilog & ISA Focus

RosaicLabs Inc; Santa Clara (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Medical (HSA)

Dental

Vision

Life & AD&D

401(k)

Job summary

RosaicLabs Inc in Santa Clara is seeking a CPU verification engineer to drive verification strategy, develop directed and pseudo-random tests, and build SystemVerilog/UVM testbenches for the CPU core and cache hierarchy.

You will collaborate with RTL design, performance modeling, and software teams to improve tools, flows, and coverage, ensuring robust tape-out readiness for next-generation CPUs.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or Computer Science.
• Strong foundation in computer architecture and digital design.
• Familiarity with at least two of: OoO execution, memory systems, cache coherency, virtual memory, SIMD.
• Proficiency in SystemVerilog, C/C++, and Python.
• Experience with ISA simulators or reference models.
• Scripting for automation and regression management.

Responsibilities

• Develop verification plans for the CPU core and cache hierarchy.
• Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block or subsystem.
• Build tests, scoreboards, and reference models, and close functional and code coverage.
• Triage and root-cause failures with RTL designers and drive bugs to resolution.
• Participate in design and verification reviews and document your verification environment and results.
• Verify the core against an ISA reference model using random instruction generation and co-simulation.

Skills

SystemVerilog

C/C++

Python

ISA knowledge

Debugging

Regression management

Education

BS/MS in Electrical/Computer Engineering or CS

Tools

UVM

Job description

RosaicLabs Inc in Santa Clara is seeking a CPU verification engineer to drive verification strategy, develop directed and pseudo-random tests, and build SystemVerilog/UVM testbenches for the CPU core and cache hierarchy.

You will collaborate with RTL design, performance modeling, and software teams to improve tools, flows, and coverage, ensuring robust tape-out readiness for next-generation CPUs.