Senior Physical Design Engineer

ACL Digital; San Jose (CA); On-site; USD 160,000 - 210,000; Full time

Job summary

ACL Digital is seeking a seasoned Physical Design Engineer to lead the implementation of high-performance RISC-V based processor designs from RTL to GDSII. You will own full-chip and block-level physical implementation, timing closure, power optimization, PPA, and sign-off across domains.

Ideal candidates have 8+ years of block-level PD experience, with hands-on work on EM/IR, power grids, floorplanning, clock-tree synthesis, and sign-off readiness using industry tools.

Qualifications

• At least 8 years of block-level physical implementation from RTL to GDSII.
• Experience with EM/IR and power grid optimization for high-current blocks.
• Experience driving sign-off: DRC, LVS, antenna, ERC, tapeout readiness.
• Experience in routing-aware floorplanning and clock-tree synthesis with skew management.
• Proficiency in Tcl, Python, Perl for PD automation.

Responsibilities

• Own full-chip and block-level physical implementation from RTL to GDSII.
• Drive timing closure and power optimization to meet PPA targets.
• Support sign-off activities: DRC, LVS, antenna, ERC, and tapeout readiness.
• Contribute to and improve physical design automation infrastructure using scripting tools.

Skills

Block-level PD experience

RTL to GDSII experience

Timing closure

Power optimization

PD sign-off

Scripting for PD (Tcl, Python, Perl)

Clock tree synthesis

Floorplanning

Tools

Innovus

ICC2

Calibre

Voltus

RedHawk

Job description

We are seeking a skilled Physical Design Engineer to implement high-performance RISC-V based processor designs from RTL to GDSII. The role involves full-chip and block-level physical implementation, timing closure, power optimization, PPA and sign-off.

Qualification and Required skills:

• Atleast 8 Years of Experience in Block-level physical implementation from RTL to GDSII
• Own advanced physical design tasks including: EM/IR and power grid optimization for high-current blocks, Congestion mitigation and routing-aware floorplanning and Clock tree synthesis and skew management across domains.
• Drive signoff closure: DRC, LVS, antenna, ERC, and tapeout readiness using industry-standard tools (e.g., Innovus, ICC2, Calibre, Voltus, RedHawk).
• Contribute to and improve physical design automation infrastructure using Tcl, Python, Perl, and other scripting tools.